From f9317213bd114bdc88facc26266b38a7edacb1f4 Mon Sep 17 00:00:00 2001 From: Ryo Shimizu Date: Thu, 23 Mar 2023 02:47:43 +0900 Subject: [PATCH 06/13] WIP: XXX: squash: add support NVMM aarch64 acceleration (3). save/restore fpregs --- target/arm/nvmm/nvmm.c | 44 +++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/target/arm/nvmm/nvmm.c b/target/arm/nvmm/nvmm.c index 88422c40bf..77c76a4432 100644 --- a/target/arm/nvmm/nvmm.c +++ b/target/arm/nvmm/nvmm.c @@ -152,8 +152,8 @@ static struct nvmm_sreg_match nvmm_sreg_match[] = { { NVMM_AARCH64_SPR_ELR_EL1, ENCODE_SYSREG( 4, 0, 3, 0, 1) }, { NVMM_AARCH64_SPR_ESR_EL1, ENCODE_SYSREG( 5, 2, 3, 0, 0) }, { NVMM_AARCH64_SPR_FAR_EL1, ENCODE_SYSREG( 6, 0, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_FPCR, ENCODE_SYSREG( 4, 4, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_FPSR, ENCODE_SYSREG( 4, 4, 3, 3, 1) }, +//EX { NVMM_AARCH64_SPR_FPCR, ENCODE_SYSREG( 4, 4, 3, 3, 0) }, +//EX { NVMM_AARCH64_SPR_FPSR, ENCODE_SYSREG( 4, 4, 3, 3, 1) }, // { NVMM_AARCH64_SPR_GCR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 6) }, // { NVMM_AARCH64_SPR_GMID_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 4) }, // { NVMM_AARCH64_SPR_ID_AA64AFR0_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 4) }, @@ -197,8 +197,8 @@ static struct nvmm_sreg_match nvmm_sreg_match[] = { // { NVMM_AARCH64_SPR_MDCCSR_EL0, ENCODE_SYSREG( 0, 1, 2, 3, 0) }, // { NVMM_AARCH64_SPR_MDRAR_EL1, ENCODE_SYSREG( 1, 0, 2, 0, 0) }, { NVMM_AARCH64_SPR_MDSCR_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 2) }, -//ERROR { NVMM_AARCH64_SPR_MIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 0) }, -//ERROR { NVMM_AARCH64_SPR_MPIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 5) }, +//EX { NVMM_AARCH64_SPR_MIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 0) }, +//EX { NVMM_AARCH64_SPR_MPIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 5) }, // { NVMM_AARCH64_SPR_MVFR0_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 0) }, // { NVMM_AARCH64_SPR_MVFR1_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 1) }, // { NVMM_AARCH64_SPR_MVFR2_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 2) }, @@ -338,18 +338,21 @@ nvmm_set_registers(CPUState *cpu) /* GPRs */ for (i = 0; i < 32; i++) { - state->gprs[NVMM_AARCH64_GPR_X0 + i ] = env->xregs[i]; + state->gprs[i] = env->xregs[i]; } + state->sprs[NVMM_AARCH64_SPR_SP_EL0] = env->sp_el[0]; + state->sprs[NVMM_AARCH64_SPR_SP_EL1] = env->sp_el[1]; + state->sprs[NVMM_AARCH64_SPR_PC] = env->pc; + state->sprs[NVMM_AARCH64_SPR_SPSR_EL1] = pstate_read(env); /* FPRs */ - //XXXXXXXXXXXXXXXXXXXXXXXXXX NOTYET - //FPCR - //FPSR + for (i = 0; i < 32; i++) { + memcpy(&state->fprs[i], &env->vfp.zregs[i], sizeof(state->fprs[i])); + } + state->sprs[NVMM_AARCH64_SPR_FPCR] = vfp_get_fpcr(env); + state->sprs[NVMM_AARCH64_SPR_FPSR] = vfp_get_fpsr(env); /* SPRs */ - state->sprs[NVMM_AARCH64_SPR_PC] = env->pc; - state->sprs[NVMM_AARCH64_SPR_SPSR_EL1] = pstate_read(env); - assert(write_cpustate_to_list(arm_cpu, false)); for (i = 0; i < ARRAY_SIZE(nvmm_sreg_match); i++) { if (nvmm_sreg_match[i].cp_idx == -1) { @@ -390,20 +393,21 @@ nvmm_get_registers(CPUState *cpu) /* GPRs */ for (i = 0; i < 32; i++) { - env->xregs[i] = state->gprs[NVMM_AARCH64_GPR_X0 + i ]; + env->xregs[i] = state->gprs[i]; } + env->sp_el[0] = state->sprs[NVMM_AARCH64_SPR_SP_EL0]; + env->sp_el[1] = state->sprs[NVMM_AARCH64_SPR_SP_EL1]; + env->pc = state->sprs[NVMM_AARCH64_SPR_PC]; + pstate_write(env, state->sprs[NVMM_AARCH64_SPR_SPSR_EL1]); /* FPRs */ - //XXXXXXXXXXXXXX NOTYET - //FPCR - //FPSR + for (i = 0; i < 32; i++) { + memcpy(&env->vfp.zregs[i], &state->fprs[i], sizeof(state->fprs[i])); + } + vfp_set_fpcr(env, state->sprs[NVMM_AARCH64_SPR_FPCR]); + vfp_set_fpsr(env, state->sprs[NVMM_AARCH64_SPR_FPSR]); /* SPRs */ - env->pc = state->sprs[NVMM_AARCH64_SPR_PC]; - pstate_write(env, state->sprs[NVMM_AARCH64_SPR_SPSR_EL1]); - env->sp_el[0] = state->sprs[NVMM_AARCH64_SPR_SP_EL0]; - env->sp_el[1] = state->sprs[NVMM_AARCH64_SPR_SP_EL1]; - for (i = 0; i < ARRAY_SIZE(nvmm_sreg_match); i++) { if (nvmm_sreg_match[i].cp_idx == -1) { continue; -- 2.54.0 (Apple Git-157)