From 5b2641ccdad2a925ba8090ef47d57ae4282463d8 Mon Sep 17 00:00:00 2001 From: Ryo Shimizu Date: Sun, 26 Mar 2023 17:32:27 +0900 Subject: [PATCH 07/13] WIP: XXX: squash: add support NVMM aarch64 acceleration (3). trapped sysreg support. sprinkle debug code. --- target/arm/cpu64.c | 24 +- target/arm/nvmm/nvmm.c | 740 ++++++++++++++++++++++++----------------- target/arm/nvmm_arm.h | 18 + 3 files changed, 478 insertions(+), 304 deletions(-) create mode 100644 target/arm/nvmm_arm.h diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2082672dea..3f1a1dc089 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -26,10 +26,12 @@ #include "qemu/units.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/nvmm.h" #include "system/qtest.h" #include "system/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "nvmm_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "internals.h" @@ -536,7 +538,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); - if (kvm_enabled() || hvf_enabled()) { + if (kvm_enabled() || hvf_enabled() || nvmm_enabled()) { /* * Exit early if PAuth is enabled and fall through to disable it. * The algorithm selection properties are not present. @@ -613,13 +615,13 @@ void aarch64_add_pauth_properties(Object *obj) /* Default to PAUTH on, with the architected algorithm on TCG. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - if (kvm_enabled() || hvf_enabled()) { + if (kvm_enabled() || hvf_enabled() || nvmm_enabled()) { /* * Mirror PAuth support from the probed sysregs back into the - * property for KVM or hvf. Is it just a bit backward? Yes it is! + * property for KVM, hvf or nvmm. Is it just a bit backward? Yes it is! * Note that prop_pauth is true whether the host CPU supports the * architected QARMA5 algorithm or the IMPDEF one. We don't - * provide the separate pauth-impdef property for KVM or hvf, + * provide the separate pauth-impdef property for KVM, hvf or nvmm, * only for TCG. */ cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); @@ -782,6 +784,13 @@ static void aarch64_host_initfn(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); } +#elif defined(CONFIG_NVMM) + nvmm_arm_set_cpu_features_from_host(cpu); +#if 0 + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + aarch64_add_sve_properties(obj); + } +#endif #elif defined(CONFIG_HVF) hvf_arm_set_cpu_features_from_host(cpu); #else @@ -794,8 +803,9 @@ static void aarch64_host_initfn(Object *obj) static void aarch64_max_initfn(Object *obj) { - if (kvm_enabled() || hvf_enabled()) { - /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ + if (kvm_enabled() || hvf_enabled() || nvmm_enabled()) { + /* With KVM, HVF or NVMM, '-cpu max' is identical to '-cpu host' */ + aarch64_host_initfn(obj); return; } @@ -814,7 +824,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_NVMM) { .name = "host", .initfn = aarch64_host_initfn }, #endif }; diff --git a/target/arm/nvmm/nvmm.c b/target/arm/nvmm/nvmm.c index 77c76a4432..889fe53a97 100644 --- a/target/arm/nvmm/nvmm.c +++ b/target/arm/nvmm/nvmm.c @@ -20,15 +20,22 @@ #include "qapi/error.h" #include "qemu/queue.h" #include "migration/blocker.h" +#include "nvmm_arm.h" #include "cpregs.h" #include "strings.h" +#include +#include + struct AccelCPUState { struct nvmm_vcpu vcpu; bool stop; }; struct nvmm_sreg_match { + int group; +#define SREG_GROUP_SPR 0 +#define SREG_GROUP_TID 1 int reg; uint32_t key; uint32_t cp_idx; @@ -38,288 +45,288 @@ struct nvmm_sreg_match { ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) static struct nvmm_sreg_match nvmm_sreg_match[] = { -// { NVMM_AARCH64_SPR_ACTLR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_AFSR0_EL1, ENCODE_SYSREG( 5, 1, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_AFSR1_EL1, ENCODE_SYSREG( 5, 1, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_AIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 7) }, - { NVMM_AARCH64_SPR_AMAIR_EL1, ENCODE_SYSREG( 10, 3, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_APDAKEYHI_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_APDAKEYLO_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_APDBKEYHI_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 3) }, -// { NVMM_AARCH64_SPR_APDBKEYLO_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_APGAKEYHI_EL1, ENCODE_SYSREG( 2, 3, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_APGAKEYLO_EL1, ENCODE_SYSREG( 2, 3, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_APIAKEYHI_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_APIAKEYLO_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_APIBKEYHI_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 3) }, -// { NVMM_AARCH64_SPR_APIBKEYLO_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_CCSIDR2_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 2) }, -// { NVMM_AARCH64_SPR_CCSIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 0) }, -// { NVMM_AARCH64_SPR_CLIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 1) }, -// { NVMM_AARCH64_SPR_CNTFRQ_EL0, ENCODE_SYSREG( 14, 0, 3, 3, 0) }, - { NVMM_AARCH64_SPR_CNTKCTL_EL1, ENCODE_SYSREG( 14, 1, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_CNTPCT_EL0, ENCODE_SYSREG( 14, 0, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_CNTPS_CTL_EL1, ENCODE_SYSREG( 14, 2, 3, 7, 1) }, -// { NVMM_AARCH64_SPR_CNTPS_CVAL_EL1, ENCODE_SYSREG( 14, 2, 3, 7, 2) }, -// { NVMM_AARCH64_SPR_CNTPS_TVAL_EL1, ENCODE_SYSREG( 14, 2, 3, 7, 0) }, -// { NVMM_AARCH64_SPR_CNTP_CTL_EL0, ENCODE_SYSREG( 14, 2, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_CNTP_CVAL_EL0, ENCODE_SYSREG( 14, 2, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_CNTP_TVAL_EL0, ENCODE_SYSREG( 14, 2, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_CNTVCT_EL0, ENCODE_SYSREG( 14, 0, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_CNTV_CTL_EL0, ENCODE_SYSREG( 14, 3, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_CNTV_CVAL_EL0, ENCODE_SYSREG( 14, 3, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_CNTV_TVAL_EL0, ENCODE_SYSREG( 14, 3, 3, 3, 0) }, - { NVMM_AARCH64_SPR_CONTEXTIDR_EL1, ENCODE_SYSREG( 13, 0, 3, 0, 1) }, - { NVMM_AARCH64_SPR_CPACR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 2) }, - { NVMM_AARCH64_SPR_CSSELR_EL1, ENCODE_SYSREG( 0, 0, 3, 2, 0) }, -// { NVMM_AARCH64_SPR_CTR_EL0, ENCODE_SYSREG( 0, 0, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_CURRENTEL, ENCODE_SYSREG( 4, 2, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_DAIF, ENCODE_SYSREG( 4, 2, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_DBGAUTHSTATUS_EL1, ENCODE_SYSREG( 7, 14, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGBCR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBCR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 5) }, -// { NVMM_AARCH64_SPR_DBGBVR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGBVR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGCLAIMCLR_EL1, ENCODE_SYSREG( 7, 9, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGCLAIMSET_EL1, ENCODE_SYSREG( 7, 8, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGDTRRX_EL0, ENCODE_SYSREG( 0, 5, 2, 3, 0) }, -// { NVMM_AARCH64_SPR_DBGDTR_EL0, ENCODE_SYSREG( 0, 4, 2, 3, 0) }, -// { NVMM_AARCH64_SPR_DBGPRCR_EL1, ENCODE_SYSREG( 1, 4, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_DBGWCR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWCR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 7) }, -// { NVMM_AARCH64_SPR_DBGWVR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DBGWVR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 6) }, -// { NVMM_AARCH64_SPR_DCZID_EL0, ENCODE_SYSREG( 0, 0, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_DIT, ENCODE_SYSREG( 4, 2, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_DLR_EL0, ENCODE_SYSREG( 4, 5, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_DSPSR_EL0, ENCODE_SYSREG( 4, 5, 3, 3, 0) }, - { NVMM_AARCH64_SPR_ELR_EL1, ENCODE_SYSREG( 4, 0, 3, 0, 1) }, - { NVMM_AARCH64_SPR_ESR_EL1, ENCODE_SYSREG( 5, 2, 3, 0, 0) }, - { NVMM_AARCH64_SPR_FAR_EL1, ENCODE_SYSREG( 6, 0, 3, 0, 0) }, -//EX { NVMM_AARCH64_SPR_FPCR, ENCODE_SYSREG( 4, 4, 3, 3, 0) }, -//EX { NVMM_AARCH64_SPR_FPSR, ENCODE_SYSREG( 4, 4, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_GCR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 6) }, -// { NVMM_AARCH64_SPR_GMID_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 4) }, -// { NVMM_AARCH64_SPR_ID_AA64AFR0_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 4) }, -// { NVMM_AARCH64_SPR_ID_AA64AFR1_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 5) }, -// { NVMM_AARCH64_SPR_ID_AA64DFR0_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_ID_AA64DFR1_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_ID_AA64ISAR0_EL1, ENCODE_SYSREG( 0, 6, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_ID_AA64ISAR1_EL1, ENCODE_SYSREG( 0, 6, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_ID_AA64MMFR0_EL1, ENCODE_SYSREG( 0, 7, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_ID_AA64MMFR1_EL1, ENCODE_SYSREG( 0, 7, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_ID_AA64MMFR2_EL1, ENCODE_SYSREG( 0, 7, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_ID_AA64PFR0_EL1, ENCODE_SYSREG( 0, 4, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_ID_AA64PFR1_EL1, ENCODE_SYSREG( 0, 4, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_ID_AFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 3) }, -// { NVMM_AARCH64_SPR_ID_DFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_ID_DFR1_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 5) }, -// { NVMM_AARCH64_SPR_ID_ISAR0_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_ID_ISAR1_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_ID_ISAR2_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_ID_ISAR3_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 3) }, -// { NVMM_AARCH64_SPR_ID_ISAR4_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 4) }, -// { NVMM_AARCH64_SPR_ID_ISAR5_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 5) }, -// { NVMM_AARCH64_SPR_ID_ISAR6_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 7) }, -// { NVMM_AARCH64_SPR_ID_MMFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 4) }, -// { NVMM_AARCH64_SPR_ID_MMFR1_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 5) }, -// { NVMM_AARCH64_SPR_ID_MMFR2_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 6) }, -// { NVMM_AARCH64_SPR_ID_MMFR3_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 7) }, -// { NVMM_AARCH64_SPR_ID_MMFR4_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 6) }, -// { NVMM_AARCH64_SPR_ID_MMFR5_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 6) }, -// { NVMM_AARCH64_SPR_ID_PFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_ID_PFR1_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_ID_PFR2_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 4) }, -// { NVMM_AARCH64_SPR_ISR_EL1, ENCODE_SYSREG( 12, 1, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_LORC_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 3) }, -// { NVMM_AARCH64_SPR_LOREA_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_LORID_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 7) }, -// { NVMM_AARCH64_SPR_LORN_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_LORSA_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 0) }, - { NVMM_AARCH64_SPR_MAIR_EL1, ENCODE_SYSREG( 10, 2, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_MDCCINT_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 0) }, -// { NVMM_AARCH64_SPR_MDCCSR_EL0, ENCODE_SYSREG( 0, 1, 2, 3, 0) }, -// { NVMM_AARCH64_SPR_MDRAR_EL1, ENCODE_SYSREG( 1, 0, 2, 0, 0) }, - { NVMM_AARCH64_SPR_MDSCR_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 2) }, -//EX { NVMM_AARCH64_SPR_MIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 0) }, -//EX { NVMM_AARCH64_SPR_MPIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 5) }, -// { NVMM_AARCH64_SPR_MVFR0_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_MVFR1_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_MVFR2_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_NZCV, ENCODE_SYSREG( 4, 2, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_OSDLR_EL1, ENCODE_SYSREG( 1, 3, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_OSDTRRX_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 2) }, -// { NVMM_AARCH64_SPR_OSDTRTX_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 2) }, -// { NVMM_AARCH64_SPR_OSECCR_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 2) }, -// { NVMM_AARCH64_SPR_OSLAR_EL1, ENCODE_SYSREG( 1, 0, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_OSLSR_EL1, ENCODE_SYSREG( 1, 1, 2, 0, 4) }, -// { NVMM_AARCH64_SPR_PAN, ENCODE_SYSREG( 4, 2, 3, 0, 3) }, - { NVMM_AARCH64_SPR_PAR_EL1, ENCODE_SYSREG( 7, 4, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_PMCCFILTR_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMCCNTR_EL0, ENCODE_SYSREG( 9, 13, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMCEID0_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMCEID1_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMCNTENCLR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMCNTENSET_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMCR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVCNTR0_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVCNTR10_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVCNTR11_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVCNTR12_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVCNTR13_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVCNTR14_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVCNTR15_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMEVCNTR16_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVCNTR17_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMEVCNTR18_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVCNTR19_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVCNTR1_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMEVCNTR20_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVCNTR21_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVCNTR22_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVCNTR23_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMEVCNTR24_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVCNTR25_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMEVCNTR26_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVCNTR27_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVCNTR28_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVCNTR29_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVCNTR2_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVCNTR30_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVCNTR3_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVCNTR4_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVCNTR5_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVCNTR6_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVCNTR7_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMEVCNTR8_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVCNTR9_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMEVTYPER0_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVTYPER10_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVTYPER11_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVTYPER12_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVTYPER13_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVTYPER14_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVTYPER15_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMEVTYPER16_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVTYPER17_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMEVTYPER18_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVTYPER19_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVTYPER1_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMEVTYPER20_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVTYPER21_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVTYPER22_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVTYPER23_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMEVTYPER24_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVTYPER25_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMEVTYPER26_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVTYPER27_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVTYPER28_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVTYPER29_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVTYPER2_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMEVTYPER30_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVTYPER3_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMEVTYPER4_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMEVTYPER5_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMEVTYPER6_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_PMEVTYPER7_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_PMEVTYPER8_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMEVTYPER9_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_PMINTENCLR_EL1, ENCODE_SYSREG( 9, 14, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_PMINTENSET_EL1, ENCODE_SYSREG( 9, 14, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_PMOVSCLR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMOVSSET_EL0, ENCODE_SYSREG( 9, 14, 3, 3, 3) }, -// { NVMM_AARCH64_SPR_PMSELR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 5) }, -// { NVMM_AARCH64_SPR_PMSWINC_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 4) }, -// { NVMM_AARCH64_SPR_PMUSERENR_EL0, ENCODE_SYSREG( 9, 14, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_PMXEVCNTR_EL0, ENCODE_SYSREG( 9, 13, 3, 3, 2) }, -// { NVMM_AARCH64_SPR_PMXEVTYPER_EL0, ENCODE_SYSREG( 9, 13, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_REVIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 6) }, -// { NVMM_AARCH64_SPR_RGSR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 5) }, -// { NVMM_AARCH64_SPR_RMR_EL1, ENCODE_SYSREG( 12, 0, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_RNDRRS, ENCODE_SYSREG( 2, 4, 3, 3, 1) }, -// { NVMM_AARCH64_SPR_RNDR, ENCODE_SYSREG( 2, 4, 3, 3, 0) }, -// { NVMM_AARCH64_SPR_RVBAR_EL1, ENCODE_SYSREG( 12, 0, 3, 0, 1) }, - { NVMM_AARCH64_SPR_SCTLR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_SCXTNUM_EL0, ENCODE_SYSREG( 13, 0, 3, 3, 7) }, -// { NVMM_AARCH64_SPR_SCXTNUM_EL1, ENCODE_SYSREG( 13, 0, 3, 0, 7) }, -// { NVMM_AARCH64_SPR_SPSEL, ENCODE_SYSREG( 4, 2, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_SPSR_ABT, ENCODE_SYSREG( 4, 3, 3, 4, 1) }, -// { NVMM_AARCH64_SPR_SPSR_EL1, ENCODE_SYSREG( 4, 0, 3, 0, 0) }, -// { NVMM_AARCH64_SPR_SPSR_FIQ, ENCODE_SYSREG( 4, 3, 3, 4, 3) }, -// { NVMM_AARCH64_SPR_SPSR_IRQ, ENCODE_SYSREG( 4, 3, 3, 4, 0) }, -// { NVMM_AARCH64_SPR_SPSR_UND, ENCODE_SYSREG( 4, 3, 3, 4, 2) }, - { NVMM_AARCH64_SPR_SP_EL0, ENCODE_SYSREG( 4, 1, 3, 0, 0) }, - { NVMM_AARCH64_SPR_SP_EL1, ENCODE_SYSREG( 4, 1, 3, 4, 0) }, -// { NVMM_AARCH64_SPR_SSBS, ENCODE_SYSREG( 4, 2, 3, 3, 6) }, -// { NVMM_AARCH64_SPR_TCO, ENCODE_SYSREG( 4, 2, 3, 3, 7) }, - { NVMM_AARCH64_SPR_TCR_EL1, ENCODE_SYSREG( 2, 0, 3, 0, 2) }, -// { NVMM_AARCH64_SPR_TEECR32_EL1, ENCODE_SYSREG( 0, 0, 2, 2, 0) }, -// { NVMM_AARCH64_SPR_TEEHBR32_EL1, ENCODE_SYSREG( 1, 0, 2, 2, 0) }, -// { NVMM_AARCH64_SPR_TFSRE0_EL1, ENCODE_SYSREG( 5, 6, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_TFSR_EL1, ENCODE_SYSREG( 5, 6, 3, 0, 0) }, - { NVMM_AARCH64_SPR_TPIDRRO_EL0, ENCODE_SYSREG( 13, 0, 3, 3, 3) }, - { NVMM_AARCH64_SPR_TPIDR_EL0, ENCODE_SYSREG( 13, 0, 3, 3, 2) }, - { NVMM_AARCH64_SPR_TPIDR_EL1, ENCODE_SYSREG( 13, 0, 3, 0, 4) }, - { NVMM_AARCH64_SPR_TTBR0_EL1, ENCODE_SYSREG( 2, 0, 3, 0, 0) }, - { NVMM_AARCH64_SPR_TTBR1_EL1, ENCODE_SYSREG( 2, 0, 3, 0, 1) }, -// { NVMM_AARCH64_SPR_UAO, ENCODE_SYSREG( 4, 2, 3, 0, 4) }, - { NVMM_AARCH64_SPR_VBAR_EL1, ENCODE_SYSREG( 12, 0, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_ACTLR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_AFSR0_EL1, ENCODE_SYSREG( 5, 1, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_AFSR1_EL1, ENCODE_SYSREG( 5, 1, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_AIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 7) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_AMAIR_EL1, ENCODE_SYSREG( 10, 3, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APDAKEYHI_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APDAKEYLO_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APDBKEYHI_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APDBKEYLO_EL1, ENCODE_SYSREG( 2, 2, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APGAKEYHI_EL1, ENCODE_SYSREG( 2, 3, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APGAKEYLO_EL1, ENCODE_SYSREG( 2, 3, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APIAKEYHI_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APIAKEYLO_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APIBKEYHI_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_APIBKEYLO_EL1, ENCODE_SYSREG( 2, 1, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CCSIDR2_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CCSIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CLIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTFRQ_EL0, ENCODE_SYSREG( 14, 0, 3, 3, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTKCTL_EL1, ENCODE_SYSREG( 14, 1, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTPCT_EL0, ENCODE_SYSREG( 14, 0, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTPS_CTL_EL1, ENCODE_SYSREG( 14, 2, 3, 7, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTPS_CVAL_EL1, ENCODE_SYSREG( 14, 2, 3, 7, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTPS_TVAL_EL1, ENCODE_SYSREG( 14, 2, 3, 7, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTP_CTL_EL0, ENCODE_SYSREG( 14, 2, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTP_CVAL_EL0, ENCODE_SYSREG( 14, 2, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTP_TVAL_EL0, ENCODE_SYSREG( 14, 2, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTVCT_EL0, ENCODE_SYSREG( 14, 0, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTV_CTL_EL0, ENCODE_SYSREG( 14, 3, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTV_CVAL_EL0, ENCODE_SYSREG( 14, 3, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CNTV_TVAL_EL0, ENCODE_SYSREG( 14, 3, 3, 3, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CONTEXTIDR_EL1, ENCODE_SYSREG( 13, 0, 3, 0, 1) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CPACR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 2) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CSSELR_EL1, ENCODE_SYSREG( 0, 0, 3, 2, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CTR_EL0, ENCODE_SYSREG( 0, 0, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_CURRENTEL, ENCODE_SYSREG( 4, 2, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DAIF, ENCODE_SYSREG( 4, 2, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGAUTHSTATUS_EL1, ENCODE_SYSREG( 7, 14, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBCR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGBVR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGCLAIMCLR_EL1, ENCODE_SYSREG( 7, 9, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGCLAIMSET_EL1, ENCODE_SYSREG( 7, 8, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGDTRRX_EL0, ENCODE_SYSREG( 0, 5, 2, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGDTR_EL0, ENCODE_SYSREG( 0, 4, 2, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGPRCR_EL1, ENCODE_SYSREG( 1, 4, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWCR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR0_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR10_EL1, ENCODE_SYSREG( 0, 10, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR11_EL1, ENCODE_SYSREG( 0, 11, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR12_EL1, ENCODE_SYSREG( 0, 12, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR13_EL1, ENCODE_SYSREG( 0, 13, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR14_EL1, ENCODE_SYSREG( 0, 14, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR15_EL1, ENCODE_SYSREG( 0, 15, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR1_EL1, ENCODE_SYSREG( 0, 1, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR2_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR3_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR4_EL1, ENCODE_SYSREG( 0, 4, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR5_EL1, ENCODE_SYSREG( 0, 5, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR6_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR7_EL1, ENCODE_SYSREG( 0, 7, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR8_EL1, ENCODE_SYSREG( 0, 8, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DBGWVR9_EL1, ENCODE_SYSREG( 0, 9, 2, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DCZID_EL0, ENCODE_SYSREG( 0, 0, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DIT, ENCODE_SYSREG( 4, 2, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DLR_EL0, ENCODE_SYSREG( 4, 5, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_DSPSR_EL0, ENCODE_SYSREG( 4, 5, 3, 3, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_ELR_EL1, ENCODE_SYSREG( 4, 0, 3, 0, 1) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_ESR_EL1, ENCODE_SYSREG( 5, 2, 3, 0, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_FAR_EL1, ENCODE_SYSREG( 6, 0, 3, 0, 0) }, +//NO_RAW { SREG_GROUP_SPR, NVMM_AARCH64_SPR_FPCR, ENCODE_SYSREG( 4, 4, 3, 3, 0) }, +//NO_RAW { SREG_GROUP_SPR, NVMM_AARCH64_SPR_FPSR, ENCODE_SYSREG( 4, 4, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_GCR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_GMID_EL1, ENCODE_SYSREG( 0, 0, 3, 1, 4) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64AFR0_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 4) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64AFR1_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 5) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64DFR0_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 0) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64DFR1_EL1, ENCODE_SYSREG( 0, 5, 3, 0, 1) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64ISAR0_EL1, ENCODE_SYSREG( 0, 6, 3, 0, 0) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64ISAR1_EL1, ENCODE_SYSREG( 0, 6, 3, 0, 1) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64MMFR0_EL1, ENCODE_SYSREG( 0, 7, 3, 0, 0) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64MMFR1_EL1, ENCODE_SYSREG( 0, 7, 3, 0, 1) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64MMFR2_EL1, ENCODE_SYSREG( 0, 7, 3, 0, 2) }, +//NO_RAW { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64PFR0_EL1, ENCODE_SYSREG( 0, 4, 3, 0, 0) }, +//NO_RAW { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AA64PFR1_EL1, ENCODE_SYSREG( 0, 4, 3, 0, 1) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_AFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 3) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_DFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 2) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_DFR1_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 5) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_ISAR0_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 0) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_ISAR1_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 1) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_ISAR2_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 2) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_ISAR3_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 3) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_ISAR4_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 4) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_ISAR5_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 5) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_ISAR6_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 7) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_MMFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 4) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_MMFR1_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 5) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_MMFR2_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 6) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_MMFR3_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 7) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_MMFR4_EL1, ENCODE_SYSREG( 0, 2, 3, 0, 6) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_MMFR5_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 6) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_PFR0_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 0) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_PFR1_EL1, ENCODE_SYSREG( 0, 1, 3, 0, 1) }, +// { SREG_GROUP_TID, NVMM_AARCH64_TID_ID_PFR2_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_ISR_EL1, ENCODE_SYSREG( 12, 1, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_LORC_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_LOREA_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_LORID_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_LORN_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_LORSA_EL1, ENCODE_SYSREG( 10, 4, 3, 0, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_MAIR_EL1, ENCODE_SYSREG( 10, 2, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_MDCCINT_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_MDCCSR_EL0, ENCODE_SYSREG( 0, 1, 2, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_MDRAR_EL1, ENCODE_SYSREG( 1, 0, 2, 0, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_MDSCR_EL1, ENCODE_SYSREG( 0, 2, 2, 0, 2) }, +//NO_RAW { SREG_GROUP_SPR, NVMM_AARCH64_SPR_MIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 0) }, +//NO_RAW { SREG_GROUP_SPR, NVMM_AARCH64_SPR_MPIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 5) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_MVFR0_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 0) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_MVFR1_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 1) }, + { SREG_GROUP_TID, NVMM_AARCH64_TID_MVFR2_EL1, ENCODE_SYSREG( 0, 3, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_NZCV, ENCODE_SYSREG( 4, 2, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_OSDLR_EL1, ENCODE_SYSREG( 1, 3, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_OSDTRRX_EL1, ENCODE_SYSREG( 0, 0, 2, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_OSDTRTX_EL1, ENCODE_SYSREG( 0, 3, 2, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_OSECCR_EL1, ENCODE_SYSREG( 0, 6, 2, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_OSLAR_EL1, ENCODE_SYSREG( 1, 0, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_OSLSR_EL1, ENCODE_SYSREG( 1, 1, 2, 0, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PAN, ENCODE_SYSREG( 4, 2, 3, 0, 3) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PAR_EL1, ENCODE_SYSREG( 7, 4, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMCCFILTR_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMCCNTR_EL0, ENCODE_SYSREG( 9, 13, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMCEID0_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMCEID1_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMCNTENCLR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMCNTENSET_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMCR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR0_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR10_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR11_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR12_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR13_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR14_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR15_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR16_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR17_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR18_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR19_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR1_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR20_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR21_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR22_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR23_EL0, ENCODE_SYSREG( 14, 10, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR24_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR25_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR26_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR27_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR28_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR29_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR2_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR30_EL0, ENCODE_SYSREG( 14, 11, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR3_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR4_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR5_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR6_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR7_EL0, ENCODE_SYSREG( 14, 8, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR8_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVCNTR9_EL0, ENCODE_SYSREG( 14, 9, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER0_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER10_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER11_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER12_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER13_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER14_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER15_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER16_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER17_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER18_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER19_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER1_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER20_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER21_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER22_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER23_EL0, ENCODE_SYSREG( 14, 14, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER24_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER25_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER26_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER27_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER28_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER29_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER2_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER30_EL0, ENCODE_SYSREG( 14, 15, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER3_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER4_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER5_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER6_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER7_EL0, ENCODE_SYSREG( 14, 12, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER8_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMEVTYPER9_EL0, ENCODE_SYSREG( 14, 13, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMINTENCLR_EL1, ENCODE_SYSREG( 9, 14, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMINTENSET_EL1, ENCODE_SYSREG( 9, 14, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMOVSCLR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMOVSSET_EL0, ENCODE_SYSREG( 9, 14, 3, 3, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMSELR_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMSWINC_EL0, ENCODE_SYSREG( 9, 12, 3, 3, 4) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMUSERENR_EL0, ENCODE_SYSREG( 9, 14, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMXEVCNTR_EL0, ENCODE_SYSREG( 9, 13, 3, 3, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_PMXEVTYPER_EL0, ENCODE_SYSREG( 9, 13, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_REVIDR_EL1, ENCODE_SYSREG( 0, 0, 3, 0, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_RGSR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 5) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_RMR_EL1, ENCODE_SYSREG( 12, 0, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_RNDRRS, ENCODE_SYSREG( 2, 4, 3, 3, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_RNDR, ENCODE_SYSREG( 2, 4, 3, 3, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_RVBAR_EL1, ENCODE_SYSREG( 12, 0, 3, 0, 1) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SCTLR_EL1, ENCODE_SYSREG( 1, 0, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SCXTNUM_EL0, ENCODE_SYSREG( 13, 0, 3, 3, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SCXTNUM_EL1, ENCODE_SYSREG( 13, 0, 3, 0, 7) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SPSEL, ENCODE_SYSREG( 4, 2, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SPSR_ABT, ENCODE_SYSREG( 4, 3, 3, 4, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SPSR_EL1, ENCODE_SYSREG( 4, 0, 3, 0, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SPSR_FIQ, ENCODE_SYSREG( 4, 3, 3, 4, 3) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SPSR_IRQ, ENCODE_SYSREG( 4, 3, 3, 4, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SPSR_UND, ENCODE_SYSREG( 4, 3, 3, 4, 2) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SP_EL0, ENCODE_SYSREG( 4, 1, 3, 0, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SP_EL1, ENCODE_SYSREG( 4, 1, 3, 4, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_SSBS, ENCODE_SYSREG( 4, 2, 3, 3, 6) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TCO, ENCODE_SYSREG( 4, 2, 3, 3, 7) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TCR_EL1, ENCODE_SYSREG( 2, 0, 3, 0, 2) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TEECR32_EL1, ENCODE_SYSREG( 0, 0, 2, 2, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TEEHBR32_EL1, ENCODE_SYSREG( 1, 0, 2, 2, 0) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TFSRE0_EL1, ENCODE_SYSREG( 5, 6, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TFSR_EL1, ENCODE_SYSREG( 5, 6, 3, 0, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TPIDRRO_EL0, ENCODE_SYSREG( 13, 0, 3, 3, 3) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TPIDR_EL0, ENCODE_SYSREG( 13, 0, 3, 3, 2) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TPIDR_EL1, ENCODE_SYSREG( 13, 0, 3, 0, 4) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TTBR0_EL1, ENCODE_SYSREG( 2, 0, 3, 0, 0) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_TTBR1_EL1, ENCODE_SYSREG( 2, 0, 3, 0, 1) }, +// { SREG_GROUP_SPR, NVMM_AARCH64_SPR_UAO, ENCODE_SYSREG( 4, 2, 3, 0, 4) }, + { SREG_GROUP_SPR, NVMM_AARCH64_SPR_VBAR_EL1, ENCODE_SYSREG( 12, 0, 3, 0, 0) }, }; /* QEMU -> NVMM */ @@ -359,7 +366,16 @@ nvmm_set_registers(CPUState *cpu) continue; } uint64_t val = arm_cpu->cpreg_values[nvmm_sreg_match[i].cp_idx]; - state->sprs[nvmm_sreg_match[i].reg] = val; + switch (nvmm_sreg_match[i].group) { + case SREG_GROUP_SPR: + state->sprs[nvmm_sreg_match[i].reg] = val; + break; + case SREG_GROUP_TID: + state->tids[nvmm_sreg_match[i].reg] = val; + break; + default: + assert(false); + } } //XXXXXXX vtimer @@ -412,7 +428,18 @@ nvmm_get_registers(CPUState *cpu) if (nvmm_sreg_match[i].cp_idx == -1) { continue; } - uint64_t val = state->sprs[nvmm_sreg_match[i].reg]; + + uint64_t val; + switch (nvmm_sreg_match[i].group) { + case SREG_GROUP_SPR: + val = state->sprs[nvmm_sreg_match[i].reg]; + break; + case SREG_GROUP_TID: + val = state->tids[nvmm_sreg_match[i].reg]; + break; + default: + assert(false); + } arm_cpu->cpreg_values[nvmm_sreg_match[i].cp_idx] = val; } assert(write_list_to_cpustate(arm_cpu)); @@ -435,10 +462,29 @@ nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { fprintf(stderr, "%s:%d: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n", __func__, __LINE__); + abort(); return 0; } +static void +nvmm_wfi(CPUState *cpu) +{ +// ARMCPU *arm_cpu = ARM_CPU(cpu); + + if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { + /* Interrupt pending, no need to wait */ + return; + } + +//XXXXX + return; + +// qatomic_mb_set(&cpu->thread_kicked, false); +// qemu_mutex_unlock_iothread(); +// pselect(0, 0, 0, 0, NULL, &cpu->hvf->unblock_ipi_mask); +// qemu_mutex_lock_iothread(); +} int nvmm_vcpu_loop(CPUState *cpu) @@ -510,6 +556,30 @@ nvmm_vcpu_loop(CPUState *cpu) case NVMM_VCPU_EXIT_MEMORY: ret = nvmm_handle_mem(mach, vcpu); break; + + case NVMM_VCPU_EXIT_MRS: + error_report("XXXXXX: NOTYET: NVMM_VCPU_EXIT_MRS\n"); + abort(); + break; + case NVMM_VCPU_EXIT_MSR: + error_report("XXXXXX: NOTYET: NVMM_VCPU_EXIT_MSR\n"); + abort(); + break; + case NVMM_VCPU_EXIT_HVC: + error_report("XXXXXX: NOTYET: NVMM_VCPU_EXIT_HVC\n"); + abort(); + break; + case NVMM_VCPU_EXIT_SMC: + error_report("XXXXXX: NOTYET: NVMM_VCPU_EXIT_SMC\n"); + abort(); + break; + case NVMM_VCPU_EXIT_WFI: + nvmm_wfi(cpu); + break; + case NVMM_VCPU_EXIT_WFE: + error_report("XXXXXX: NOTYET: NVMM_VCPU_EXIT_WFE\n"); + break; + case NVMM_VCPU_EXIT_HALTED: ret = nvmm_handle_halted(mach, cpu, exit); break; @@ -581,8 +651,6 @@ nvmm_sreg_init(CPUState *cpu) ARMCPU *arm_cpu = ARM_CPU(cpu); CPUArchState *env = cpu_env(cpu); AccelCPUState *qcpu = cpu->accel; - struct nvmm_vcpu *vcpu = &qcpu->vcpu; - struct nvmm_aarch64_state *state = vcpu->state; uint32_t sregs_match_len = ARRAY_SIZE(nvmm_sreg_match); uint32_t sregs_cnt = 0; @@ -610,6 +678,7 @@ nvmm_sreg_init(CPUState *cpu) ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); if (ri) { +// printf("group=%d, reg=%d\n", nvmm_sreg_match[i].group, nvmm_sreg_match[i].reg); assert(!(ri->type & ARM_CP_NO_RAW)); nvmm_sreg_match[i].cp_idx = sregs_cnt; arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); @@ -621,19 +690,78 @@ nvmm_sreg_init(CPUState *cpu) arm_cpu->cpreg_vmstate_array_len = sregs_cnt; assert(write_cpustate_to_list(arm_cpu, false)); - /* Set CP_NO_RAW system registers on init */ - state->sprs[NVMM_AARCH64_SPR_MIDR_EL1] = arm_cpu->midr; - state->sprs[NVMM_AARCH64_SPR_MPIDR_EL1] = arm_cpu->mp_affinity; +} -#if 0 //XXXXXXXXXXXXXXXXX - uint64_t pfr = state->sprs[NVMM_AARCH64_SPR_ID_AA64PFR0_EL1]; - pfr &= ~ID_AA64PFR0_EL1_GIC; - pfr |= __SHIFTIN(env->gicv3state ? 1 : 0, ID_AA64PFR0_EL1_GIC); - state->sprs[NVMM_AARCH64_SPR_ID_AA64PFR0_EL1] = pfr; - /* We're limited to underlying hardware caps, override internal versions */ - state->sprs[NVMM_AARCH64_SPR_ID_AA64MMFR0_EL1] = arm_cpu->isar.id_aa64mmfr0; -#endif +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; + +void +nvmm_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (arm_host_cpu_features.dtb_compatible == NULL) { + char path[128]; + size_t len; + uint64_t sysctlbuf[64]; + struct aarch64_sysctl_cpu_id *id = + (struct aarch64_sysctl_cpu_id *)sysctlbuf; + + /* + * XXX: It is necessary to get "machdep.cpuN.cpu_id" of all CPUs, + * and select the minimum feature. + */ + snprintf(path, sizeof(path), "machdep.cpu%d.cpu_id", 0); + len = sizeof(sysctlbuf); + memset(sysctlbuf, 0, len); + if (sysctlbyname(path, id, &len, 0, 0) == -1) { + error_report("couldn't get %s", path); + return; + } + if (len != sizeof(struct aarch64_sysctl_cpu_id)) { + error_report("Warning: kernel version bumped?"); + return; + } + + arm_host_cpu_features.midr = id->ac_midr; + arm_host_cpu_features.isar.idregs[ID_AA64DFR0_EL1_IDX] = id->ac_aa64dfr0; + arm_host_cpu_features.isar.idregs[ID_AA64DFR1_EL1_IDX] = id->ac_aa64dfr1; + arm_host_cpu_features.isar.idregs[ID_AA64ISAR0_EL1_IDX] = id->ac_aa64isar0; + arm_host_cpu_features.isar.idregs[ID_AA64ISAR1_EL1_IDX] = id->ac_aa64isar1; + arm_host_cpu_features.isar.idregs[ID_AA64MMFR0_EL1_IDX] = id->ac_aa64mmfr0; + arm_host_cpu_features.isar.idregs[ID_AA64MMFR1_EL1_IDX] = id->ac_aa64mmfr1; + arm_host_cpu_features.isar.idregs[ID_AA64MMFR2_EL1_IDX] = id->ac_aa64mmfr2; + arm_host_cpu_features.isar.idregs[ID_AA64PFR0_EL1_IDX] = id->ac_aa64pfr0; + arm_host_cpu_features.isar.idregs[ID_AA64PFR1_EL1_IDX] = id->ac_aa64pfr1; + arm_host_cpu_features.isar.idregs[ID_AA64ZFR0_EL1_IDX] = id->ac_aa64zfr0; + arm_host_cpu_features.isar.idregs[MVFR0_EL1_IDX] = id->ac_mvfr0; + arm_host_cpu_features.isar.idregs[MVFR1_EL1_IDX] = id->ac_mvfr1; + arm_host_cpu_features.isar.idregs[MVFR2_EL1_IDX] = id->ac_mvfr2; + + arm_host_cpu_features.isar.idregs[ID_AA64SMFR0_EL1_IDX] = 0; + arm_host_cpu_features.isar.reset_pmcr_el0 = 0; + arm_host_cpu_features.reset_sctlr = SCTLR_RES1; + + arm_host_cpu_features.dtb_compatible = "arm,arm-v8"; + arm_host_cpu_features.features = (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | +// (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + } + + /* arm_host_cpu_features to cpu */ + cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; + cpu->isar = arm_host_cpu_features.isar; + cpu->env.features = arm_host_cpu_features.features; + cpu->midr = arm_host_cpu_features.midr; + cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; } int @@ -683,9 +811,27 @@ nvmm_init_vcpu(CPUState *cpu) } cpu->vcpu_dirty = true; + cpu->accel = qcpu; nvmm_sreg_init(cpu); + /* Set CP_NO_RAW system registers on init */ + struct nvmm_aarch64_state *state = qcpu->vcpu.state; + ARMCPU *arm_cpu = ARM_CPU(cpu); + ret = nvmm_vcpu_getstate(mach, &qcpu->vcpu, NVMM_AARCH64_STATE_ALL); + + state->sprs[NVMM_AARCH64_SPR_MIDR_EL1] = arm_cpu->midr; + state->sprs[NVMM_AARCH64_SPR_MPIDR_EL1] = (1U << 31) | arm_cpu->mp_affinity; + + CPUArchState *env = &arm_cpu->env; + uint64_t pfr = state->tids[NVMM_AARCH64_TID_ID_AA64PFR0_EL1]; + pfr &= ~ID_AA64PFR0_EL1_GIC; + pfr |= __SHIFTIN(env->gicv3state ? 1 : 0, ID_AA64PFR0_EL1_GIC); + state->tids[NVMM_AARCH64_TID_ID_AA64PFR0_EL1] = pfr; + + /* We're limited to underlying hardware caps, override internal versions */ + arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX] = state->tids[NVMM_AARCH64_TID_ID_AA64MMFR0_EL1]; + return 0; } diff --git a/target/arm/nvmm_arm.h b/target/arm/nvmm_arm.h new file mode 100644 index 0000000000..66f1299d1a --- /dev/null +++ b/target/arm/nvmm_arm.h @@ -0,0 +1,18 @@ +/* + * NetBSD Virtual Machine Monitor (NVMM) support -- ARM specifics + * + * Copyright (c) 2023 Ryo Shimizu + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef QEMU_NVMM_ARM_H +#define QEMU_NVMM_ARM_H + +#include "cpu.h" + +void nvmm_arm_set_cpu_features_from_host(ARMCPU *cpu); + +#endif /* QEMU_NVMM_ARM_H */ -- 2.54.0 (Apple Git-157)